LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY rs IS
PORT(
     r,s:IN STD_LOGIC;
     q,qb:OUT STD_LOGIC);
END rs; 
ARCHITECTURE rsf OF rs IS
SIGNAL q_s,qb_s:STD_LOGIC;
BEGIN
    qb_s<=NOT (q_s and s);
    q_s<=NOT (qb_s and r);
    q<=qb_s;
    qb<=q_s;
END rsf; 





